Referring now to FIG. 1, a typical prior art inverter circuit 10 includes a P-channel transistor 12 having a gate coupled to the VIN input, a source coupled to VDD, and a drain coupled to the VOUT output. Inverter 10 also includes an N-channel transistor 14 having a gate coupled to the VIN input, a source coupled to ground, and a drain coupled to the VOUT output.
The problem with inverter 10 is that, because there is no hysteresis, it is sensitive to input noise centered around threshold voltage Vth. Referring to FIG. 2, the input vs. output characteristics 20 are shown wherein the VOUT voltage switches as the VIN voltage increases past the Vth threshold voltage. Referring to the timing diagram 30 of FIG. 3, a noisy VIN voltage pulse results in a VOUT voltage that unacceptably switches frequently at the rising and trailing edge of the input pulse.
As is known in the art, Schmitt trigger circuits having hysteresis can significantly improve the switching characteristics of the basic inverter shown in FIG. 1. Prior art Schmitt trigger circuits are shown in FIGS. 4, 6, and 7.
Referring now to FIG. 4, a first prior art Schmitt trigger circuit 40 includes a plurality of P-channel and N-channel transistors. A first P-channel transistor P1 has a gate coupled to the IN input node, a source coupled to VDD, and a drain coupled to the Vx node. A second P-channel transistor P2 has a gate coupled to the IN input node, a source coupled to the Vx node, and a drain coupled to the OUT output node. A third P-channel transistor has a gate coupled to the OUT output node, and a current path coupled between the Vx node and ground. A first N-channel transistor has a gate coupled to the IN input node, a source coupled to ground, and a drain coupled to the Vy node. A second N-channel transistor has a gate coupled to the IN input node, a source coupled to the Vy node, and a drain coupled to the OUT output node. A third N-channel transistor has a gate coupled to the OUT output node, and a current path coupled between the Vy node and VDD.
Referring now to FIG. 5, the timing diagram 50 reveals that the output voltage VOUT switches cleanly in response to the noisy VIN input pulse, and the switching problems with the prior art inverter shown in FIG. 1 are solved. However, the circuit 40 shown in FIG. 4 cannot operate at low supply voltages, cannot operate at high speeds, and the hysteresis critically depends on the supply voltage.
Referring now to FIG. 6, a second prior art Schmitt trigger circuit 60 includes a first inverter having an input coupled to the IN input voltage, and a second inverter having an input coupled to the IN input voltage. The gate of a first P-channel transistor is coupled to the output of the first inverter at the GP node. The current path of the first P-channel transistor is coupled between VDD and the Vx node. The gate of a first N-channel transistor is coupled to the output of the second inverter at the GN node. The current path of the first N-channel transistor is coupled between the Vx node and ground. An output diode circuit including three inverters INV4, INV5, and INV6 is coupled between the Vx node and the OUT output node.
In circuit 60 the threshold voltages of the first and second inverters (INV1 and INV2) decides the circuit hysteresis, which is highly PVT″ (i.e., process/supply voltage/temperature variation) sensitive. There are higher delays with Schmitt trigger circuit 60 because nodes GP and GN can become very capacitive. In addition, circuit 60 has a large area that is unsuitable for integration.
A third prior art Schmitt trigger circuit 70 is shown in FIG. 7 and is very similar to the one shown in FIG. 6. However, the inverter circuit coupled to node Vx includes only two serially connected inverters: INV4 coupled to INV6 at the Vy node. The inverter latch in FIG. 6 is removed. This allows circuit 70 to go to a floating state before any transition occurs. In turn, this results in a reduced delay as compared to prior art circuit 60, but also results in a severely reduced hysteresis.
What is desired, therefore, is a Schmitt trigger circuit that overcomes the limitations of the prior art, while having an effective hysteresis function and is suitable for integration by having a minimum die area.